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Research Interests

Computer Systems Research, Security and Privacy, MLSys

I am a computer architect working at the intersection of hardware-software co-design, privacy, and AI systems. As AI systems grow more complex and pervasive, privacy and safety cannot be an afterthought, it demands the same rigor as performance. My work spans formal privacy models, secure and homomorphic computation, architecture modeling and agile hardware tooling, and privacy-preserving computer vision for augmented reality, with publications in top venues including ISCA, ASPLOS, PLDI, FPL, and TMLR.

My SoK on hardware-software-security codesign was cited in the US National Strategy on Microelectronics Research. I am a Rising Stars in EECS alumna, and trace wringing was recognized as an IEEE Micro Top Pick.

Education

University of California, Santa Barbara
Thesis: "A System-level Framework for Privacy"
Advised by Prof. Timothy Sherwood

University of California, Santa Barbara

Ramaiah Institute of Technology, Bangalore, India

Awards and Honors

Experience

• Neural tracing: Co-developed neural tracing for mechanistic interpretability of LLMs and bio-foundation models. Submitted patent application "Model Optimization and Data Analysis Using Neural Traces" (P2)

• Distributed Intelligence and On-device AI: Prototyped gesture interaction for smart glasses (data collection, model training, compression, and demo) on SoC with custom and off-the-shelf accelerators. Through HW/SW codesign and energy-aware scheduling, my pipeline improved latency and power (by 93% & 74%)
• Performance and Power Modeling: Built Python-based system-level power and performance modeling tool for Project Aria and other wearable devices using discrete-event simulation. The system latency and power was calibrated against measurements on prototype devices running machine perception pipelines: eye tracking, hand and gesture tracking, localization and mapping.
• Hardware-Software-Security Codesign in Extended Reality: Developed security and privacy research program for mixed and augmented reality, establishing threat models for codec avatars, privately crowdsourced data collection for world modeling, and other extended reality applications; published in HASP 2020, PLDI 2021, BMVC 2021, TMLR 2025

• Trace Wringing: Developed trace wringing for safer program behavior sharing, achieving privacy through lossy compression and information flow tracking with verifiable leakage bounds; published in ASPLOS 2019, SEED 2020 and recognized as IEEE Micro Top Pick
• Agile Hardware Development with PyRTL: Co-developed PyRTL, a Pythonic hardware development toolkit enabling rapid prototyping and agile hardware design; published in FPL 2017 and IEEE Micro 2020
• Architecture Modeling with Charm: Worked on Charm, a domain-specific language for high-level architecture modeling; published in ISCA 2018, JETC 2019
• OpenTPU: Led development in PyRTL, creating open-source tensor processing unit implementation

• Implemented novel reverse engineering attack on local feature descriptors, surpassing state-of-the-art reconstruction accuracy for user image recovery
• Established first privacy threat model for computer vision feature descriptor sharing in AR systems
• Developed privacy-preserving mitigation techniques and studied effects on downstream vision system performance; published in BMVC 2021

• Implemented parameterizable architecture-aware machine learning graph primitives for custom hardware instructions on Brainwave Neural Processing Unit
• Built tools for automatic lifting of hardware instructions to high-level graph primitives while maintaining hardware fidelity
• Designed computational pipeline for NPU model decompilation with accuracy verification; resulted in patent

• Established testing environment for measuring throughput of RAPID Data Processing Unit (DPU) network, a bandwidth-optimized big data computation architecture
• Implemented network congestion tests for best/worst case traffic using hardware RPC acceleration mechanisms

Publications

[C]=Conference, [J]=Journal or Magazine, [W]=Workshop

[W4]: The Need for Computational Pluralism
D. Dangwal, A. Rajagopal.
Workshop on Ethical Systems and Architecture Design (HotEthics), 2026

[J4]: Unlocking Visual Secrets: Inverting Features with Diffusion Priors for Image Reconstruction
S. Q. Zhang, Z. Li, C. Guo, S. Mahloujifar, D. Dangwal, E. Suh, B. D. Salvo, C. Liu.
Transactions on Machine Learning Research (TMLR), 2025

[C6]: Context-Aware Privacy-Optimizing Address Tracing
D. Dangwal, Z. Zhang, J. Crandall, T. Sherwood.
IEEE International Symposium on Secure and Private Execution Environment Design (SEED), 2021

[C5]: Porcupine: A Synthesizing Compiler for Vectorized Homomorphic Encryption
M. Cowan, D. Dangwal, A. Alaghi, C. Trippel, V. T. Lee, B. Reagen.
Programming Language Design and Implementation (PLDI), 2021

[C4]: Mitigating Reverse Engineering Attacks on Local Feature Descriptors
D. Dangwal, V. T. Lee, H. J. Kim, T. Shen, M. Cowan, R. Shah, C. Trippel, B. Reagen, T. Sherwood, V. Balntas, A. Alaghi, E. Ilg.
British Machine Vision Conference (BMVC), 2021

[W3]: SoK: Opportunities for Software-Hardware-Security Codesign for Next Generation Secure Computing
D. Dangwal, M. Cowan, A. Alaghi, V. Lee, B. Reagen, C. Trippel.
Hardware and Architectural Support for Security and Privacy (HASP), 2020

[J3]: Agile Hardware Development and Instrumentation with PyRTL
D. Dangwal, G. Tzimpragos, T. Sherwood.
IEEE Micro Special Topics on Agile & Open Source Hardware, 2020

[J2]: Trace Wringing for Program Trace Privacy
D. Dangwal, W. Cui, J. McMahan, T. Sherwood.
IEEE Micro's Top Picks from Computer Architecture Conferences, 2020 (IEEE Micro Top Pick)

[C3]: Safer Program Behavior Sharing through Trace Wringing
D. Dangwal, W. Cui, J. McMahan, T. Sherwood.
Architectural Support for Programming Languages and Operating Systems (ASPLOS), 2019

[J1]: Language Support for Navigating Architecture Design in Closed Form
W. Cui, G. Tzimpragos, Y. Tao, J. McMahan, D. Dangwal, N. Tsiskaridze, G. Michelogiannakis, D. Vasudevan, T. Sherwood.
ACM Journal on Emerging Technologies in Computing Systems (JETC), 2019

[W2]: PyRTLMatrix: an Object-Oriented Hardware Design Pattern for Prototyping ML Accelerators
D. Aboye, D. Kupsh, M. Lim, J. Mai, D. Dangwal, D. Mirza, T. Sherwood.
Workshop on Energy Efficient Machine Learning and Cognitive Computing for Embedded Applications (EMC2), 2019

[W1]: PyRTL in Early Undergraduate Research
D. Mirza, D. Dangwal, T. Sherwood.
Workshop on Computer Architecture Education (WCAE), 2019

[C2]: Charm: A Language for Closed-form High-level Architecture Modeling
W. Cui, Y. Ding, D. Dangwal, A. Holmes, J. McMahan, A. JavadiAbhari, G. Tzimpragos, F. Chong, T. Sherwood.
International Symposium on Computer Architecture (ISCA), 2018

[C1]: A Pythonic Approach for Rapid Hardware Prototyping and Instrumentation
J. Clow, G. Tzimpragos, D. Dangwal, S. Guo, J. McMahan, T. Sherwood.
International Conference on Field-Programmable Logic and Applications (FPL), 2017

Pre-Prints, Reports, Articles

[A2]: Mechanism Design for Improving Hardware Security Workshop Report
CCC Workshop Report, August 2022

[A1]: Analysis and Mitigations of Reverse Engineering Attacks on Local Feature Descriptors
D. Dangwal, V. T. Lee, H. J. Kim, T. Shen, M. Cowan, R. Shah, C. Trippel, B. Reagen, T. Sherwood, V. Balntas, A. Alaghi, E. Ilg.
arXiv preprint, May 2021

Patents

[P2]: Model Optimization and Data Analysis Using Neural Traces
A. Rajagopal, G. H. Huynh, D. Dangwal
Provisional Patent Filed September 2025

[P1]: Deriving a concordant software neural network layer from a quantized firmware neural network layer
J. Fowers, D. Lo, D. Dangwal
US Patent 11556764B2, Microsoft Technology Licensing LLC, 2023

Teaching and Mentorship

• Students published "PyRTLMatrix: an Object-Oriented Hardware Design Pattern for Prototyping ML Accelerators" at EMC2 workshop
• Awarded university-wide Fiona and Michael Goodchild Graduate Mentoring Award for excellence in mentorship

Students Mentored: Joann Chen (Research Intern, Meta, 2022), Manu Kondapaneni (2020), Junayed Naushad (2019), Dawit Aboye (2018-2019), Dylan Kupsh (2018-2019), Maggi Lim (2018-2019), Jacqueline Mai (2018-2019), Angela Yung (2016-2017), Saurabh Gupta (2015)

Invited Talks and Seminars

Professional Service and Activities

• Represented CRA and Washington State in Washington, D.C., and joined meetings with Members of Congress to make the case for federal support of computing research

Updated March 2026