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Research Summary

Computer architect specializing in hardware-software co-design for safe and energy-efficient systems. Pioneer in system-level privacy with "trace wringing" framework (IEEE Micro Top Pick) and novel threat models for visual feature descriptors. Created widely-used tools including PyRTL, Charm, and OpenTPU. Rising Stars in EECS recipient with 13 publications in top-tier venues (ISCA, ASPLOS, PLDI).

Most recently advancing low-power, always-on, wearable computing at Meta Reality Labs Research, enabling latency and power savings via distributed architectures and model compression.

Education

University of California, Santa Barbara

University of California, Santa Barbara

M. S. Ramaiah Institute of Technology, Bangalore, India

Awards and Honors

Experience

• Led innovation in energy-efficient system design for AR/smart glasses, achieving 93% latency improvements and 74% power reduction through strategic compute placement and model compression
• Invented novel low-power always-on event-based wake-up system using hand gestures on custom accelerators for optimized smart glasses interactions
• Built system-level power and performance modeling tool for Aria wearable devices using discrete-event simulation
• Developed security and privacy research program for mixed and augmented reality, establishing threat models for codec avatars, crowdsourced data collection; published in BMVC 2021, TMLR 2025

• Developed trace wringing framework for safer program behavior sharing, achieving privacy through extreme lossy compression with verifiable leakage bounds; published in ASPLOS 2019 and recognized as IEEE Micro Top Pick
• Co-developed PyRTL, a Pythonic hardware development toolkit enabling rapid prototyping and agile hardware design; published in FPL 2017 and IEEE Micro 2020
• Worked on Charm, a domain-specific language for closed-form high-level architecture modeling; published in ISCA 2018
• Led OpenTPU development in PyRTL, creating open-source tensor processing unit implementation

• Implemented novel reverse engineering attack on local feature descriptors, surpassing state-of-the-art reconstruction accuracy for user image recovery
• Established first privacy threat model for computer vision feature descriptor sharing in AR systems
• Developed privacy-preserving mitigation techniques and studied effects on downstream vision system performance; published in BMVC 2021

• Implemented parameterizable architecture-aware machine learning graph primitives for custom hardware instructions on Brainwave Neural Processing Unit
• Built tools for automatic conversion of hardware instructions to high-level graph primitives while maintaining hardware fidelity
• Designed computational experiments for neural network model accuracy verification; resulted in patent

• Established testing environment for measuring throughput of RAPID Data Processing Unit (DPU) network, a bandwidth-optimized big data computation architecture
• Implemented network congestion tests for best and worst case traffic conditions using hardware RPC acceleration mechanisms

Publications

[C]=Conference, [J]=Journal or Magazine, [W]=Workshop

[J4]: Unlocking Visual Secrets: Inverting Features with Diffusion Priors for Image Reconstruction
S. Q. Zhang, Z. Li, C. Guo, S. Mahloujifar, D. Dangwal, E. Suh, B. D. Salvo, C. Liu.
Transactions on Machine Learning Research (TMLR), 2025

[C6]: Context-Aware Privacy-Optimizing Address Tracing
D. Dangwal, Z. Zhang, J. Crandall, T. Sherwood.
IEEE International Symposium on Secure and Private Execution Environment Design (SEED), 2021

[C5]: Porcupine: A Synthesizing Compiler for Vectorized Homomorphic Encryption
M. Cowan, D. Dangwal, A. Alaghi, C. Trippel, V. T. Lee, B. Reagen.
Programming Language Design and Implementation (PLDI), 2021

[C4]: Mitigating Reverse Engineering Attacks on Local Feature Descriptors
D. Dangwal, V. T. Lee, H. J. Kim, T. Shen, M. Cowan, R. Shah, C. Trippel, B. Reagen, T. Sherwood, V. Balntas, A. Alaghi, E. Ilg.
British Machine Vision Conference (BMVC), 2021

[W3]: SoK: Opportunities for Software-Hardware-Security Codesign for Next Generation Secure Computing
D. Dangwal, M. Cowan, A. Alaghi, V. Lee, B. Reagen, C. Trippel.
Hardware and Architectural Support for Security and Privacy (HASP), 2020

[J3]: Agile Hardware Development and Instrumentation with PyRTL
D. Dangwal, G. Tzimpragos, T. Sherwood.
IEEE Micro Special Topics on Agile & Open Source Hardware, 2020

[J2]: Trace Wringing for Program Trace Privacy
D. Dangwal, W. Cui, J. McMahan, T. Sherwood.
IEEE Micro's Top Picks from Computer Architecture Conferences, 2020 (IEEE Micro Top Pick)

[C3]: Safer Program Behavior Sharing through Trace Wringing
D. Dangwal, W. Cui, J. McMahan, T. Sherwood.
Architectural Support for Programming Languages and Operating Systems (ASPLOS), 2019

[J1]: Language Support for Navigating Architecture Design in Closed Form
W. Cui, G. Tzimpragos, Y. Tao, J. McMahan, D. Dangwal, N. Tsiskaridze, G. Michelogiannakis, D. Vasudevan, T. Sherwood.
ACM Journal on Emerging Technologies in Computing Systems (JETC), 2019

[W2]: PyRTLMatrix: an Object-Oriented Hardware Design Pattern for Prototyping ML Accelerators
D. Aboye, D. Kupsh, M. Lim, J. Mai, D. Dangwal, D. Mirza, T. Sherwood.
Workshop on Energy Efficient Machine Learning and Cognitive Computing for Embedded Applications (EMC2), 2019

[W1]: PyRTL in Early Undergraduate Research
D. Mirza, D. Dangwal, T. Sherwood.
Workshop on Computer Architecture Education (WCAE), 2019

[C2]: Charm: A Language for Closed-form High-level Architecture Modeling
W. Cui, Y. Ding, D. Dangwal, A. Holmes, J. McMahan, A. JavadiAbhari, G. Tzimpragos, F. Chong, T. Sherwood.
International Symposium on Computer Architecture (ISCA), 2018

[C1]: A Pythonic Approach for Rapid Hardware Prototyping and Instrumentation
J. Clow, G. Tzimpragos, D. Dangwal, S. Guo, J. McMahan, T. Sherwood.
International Conference on Field-Programmable Logic and Applications (FPL), 2017

Pre-Prints, Reports, Articles

[A3]: Unlocking Visual Secrets: Inverting Features with Diffusion Priors for Image Reconstruction
S. Q. Zhang, Z. Li, C. Guo, S. Mahloujifar, D. Dangwal, E. Suh, B. D. Salvo, C. Liu.
arXiv preprint, December 2024

[A2]: Mechanism Design for Improving Hardware Security Workshop Report
CCC Workshop Report, August 2022

[A1]: Analysis and Mitigations of Reverse Engineering Attacks on Local Feature Descriptors
D. Dangwal, V. T. Lee, H. J. Kim, T. Shen, M. Cowan, R. Shah, C. Trippel, B. Reagen, T. Sherwood, V. Balntas, A. Alaghi, E. Ilg.
arXiv preprint, May 2021

Patents

[P1]: Deriving a concordant software neural network layer from a quantized firmware neural network layer
J. Fowers, D. Lo, D. Dangwal
US Patent 11556764B2, Microsoft Technology Licensing LLC, 2023

Teaching and Mentorship

• Mentored team of four UCSB Computer Science sophomores on year-long research project
• Students published "PyRTLMatrix: an Object-Oriented Hardware Design Pattern for Prototyping ML Accelerators" at EMC2 workshop
• Awarded university-wide Fiona and Michael Goodchild Graduate Mentoring Award for excellence in mentorship

Students Mentored: Joann Chen (2022), Manu Kondapaneni (2020), Junayed Naushad (2019), Dawit Aboye (2018-2019), Dylan Kupsh (2018-2019), Maggi Lim (2018-2019), Jacqueline Mai (2018-2019), Angela Yung (2016-2017), Saurabh Gupta (2015)

Talks and Seminars

Meta, Reality Labs Research
Arizona State University, Phoenix
Pennsylvania State University, College Station

Professional Service and Activities

Conference Attendance: Grace Hopper Celebration of Women (2017, 2018, 2019), CRA-W Grad Cohort (2017, 2018)

Last updated: July 2025